As integrated circuits become increasingly compact, processing dimensions continue to shrink. One result of shrinking process dimensions is the impact of parasitic capacitance and parasitic capacitance variations within the integrated circuit. Parasitic capacitance can be described as capacitance that is not taken into account when considering ideal circuit elements. Parasitic capacitance causes operating anomalies in the integrated circuit and when severe, can cause the integrated circuit to malfunction, or function at a level below its intended performance level. The effects of parasitic capacitance become more significant as the physical size of the circuitry is made smaller.
When an integrated circuit is designed, capacitance values are calculated based on the performance of ideal circuit elements and the values for parasitic capacitances are estimated based on factors such as the physical layout of the circuit. However, when the circuit is fabricated, process variations, such as physical size of conductors and traces, process variation over time, temperature variations, and other variations in the processing of the integrated circuit, give rise to parasitic capacitance variation. Further, variations in parasitic capacitances over two or more identically designed portions of the integrated circuit reduce the performance of the circuit and make circuit performance even more difficult to predict.
Therefore, it would be desirable to have a way to determine capacitance variations over an integrated circuit.